Measurement and modelling of 1/f noise in 180 nm NMOS and PMOS devices

Bias dependence and scaling of 1/f noise is an important subject for the design of analog/RF integrated circuits in scaled CMOS technology. In this paper, we report on the behavior of low frequency noise, including experimental characterization and compact modeling for NMOS and PMOS devices in 180 nm CMOS technology. Aspects of bias dependence and scaling are examined. Input referred noise shows an important increase in strong inversion and a minimum in moderate inversion. The compact model approach is based on the charge-based model, including carrier number fluctuation, mobility fluctuation and resistance fluctuation noise mechanisms. The low frequency noise model is related closely to the underlying charge-based model, and is implemented in the context of the EKV3 compact MOSFET model. As a result, 1/f noise bias dependence and scaling is covered over a wide range of geometry and bias, ranging from long- to short-channel and weak to strong inversion conditions.