Title :
The experience of use of VHDL synthesis in designing radio frequency identification system
Author :
Zaitsau, Viktor ; Stepanets, Vladimir
Author_Institution :
Math. Cybern. Dept., Belarusian State Univ., Minsk, Belarus
Abstract :
In this paper the experience of use of VHDL description and synthesis of digital blocks of RFID system for transport is described.
Keywords :
block codes; finite state machines; hardware description languages; network synthesis; radiofrequency identification; VHDL synthesis; coding block; digital block synthesis; finite state machines; radio frequency identification system; EPROM; Encoding; Frequency modulation; Integrated circuits; Libraries; Logic gates; Radiofrequency identification; RFID system; VHDL description; VHDL synthesis;
Conference_Titel :
CAD Systems in Microelectronics (CADSM), 2011 11th International Conference The Experience of Designing and Application of
Conference_Location :
Polyana-Svalyava
Print_ISBN :
978-1-4577-0042-2
