Title :
Selection of Functional Test Sequences With Overlaps
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Functional test sequences may be generated for simulation-based design verification, and used as manufacturing tests or for speed binning. A class of earlier procedures selects functional test sequences for target faults from a set of available sequences in order to reduce the storage requirements and test application time. This paper describes a procedure that reduces the storage requirements further by using the selected sequences for producing additional sequences, which are referred to as overlaps. In an overlap, the first vectors of one selected sequence and the last vectors of another are combined. Overlaps thus combine initialization, fault activation and fault propagation conditions from two sequences to detect additional faults, making it unnecessary to select other sequences. Overlaps can also be used for increasing the fault coverage with respect to a fault model that was not targeted during the selection of the sequences.
Keywords :
automatic test pattern generation; fault diagnosis; integrated circuit testing; combine initialization; fault activation; fault propagation; functional test sequence selection; sequence overlap; simulation based design verification; storage reduction; target fault; Circuit faults; Compaction; Computational modeling; Delays; Manufacturing; Silicon; Vectors; Functional test sequences; single stuck-at faults; test sequence selection; test sequence storage; transition faults;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2013.2293473