Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

Author

Maheshwaram, Satish ; Manhas, Sanjeev Kumar ; Kaushal, Gaurav ; Anand, B. ; Singh, Navab

Author_Institution

Dept. of Electron. & Commun. Eng., Indian Inst. of Technol., Roorkee, Roorkee, India

Volume

60

Issue

9

fYear

2013

fDate

Sept. 2013

Firstpage

2943

Lastpage

2950

Abstract

In this paper, the analytical models of parasitic resistance and capacitance of vertical nanowire (VNW) FET are presented, considering device structural asymmetry. These models are then used to analyze the effect of channel, source-drain extension lengths, and nanowire diameter on device and VNW CMOS performance for 15 nm node. We find that the asymmetry in structure (between top and bottom electrodes) leads to asymmetric parasitic resistances and capacitances that play an important role in determining the circuit delays. Thus our models help to quantify the role of parasitics on VNW device and CMOS performance having device asymmetry. Further, these parasitic models have high potential for use in developing a compact model of a complete device for VNW circuit simulations.

Keywords

CMOS integrated circuits; field effect transistors; nanowires; semiconductor device models; VNW CMOS; VNW FET; VNW circuit simulation; asymmetric parasitic resistance; circuit delay; device structural asymmetry; electrodes; nanowire diameter; parasitic capacitance; size 15 nm; source-drain extension length; vertical nanowire CMOS parasitic modeling; Capacitance; Integrated circuit modeling; Logic gates; MOS devices; Metals; Resistance; Semiconductor device modeling; Inverter delay; modeling; parasitic capacitance; parasitic resistance; vertical nanowire MOSFET;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2013.2272651

Filename

6566064