DocumentCode
545678
Title
Impacting verification closure using formal analysis
Author
Roselli, Massimo
Author_Institution
Cadence Design Syst., Rozzano, Italy
fYear
2010
fDate
20-23 Oct. 2010
Firstpage
271
Lastpage
271
Abstract
Formal Analysis has been living in its own world. Its impact on the mainstream simulation was limited. In particular the results and metrics generated by Formal could not be factored into the simulation flow. In IEV we include a mechanism to translate formal result into simulation results and therefore enable contributions from the Formal Analysis effort to be accounted for in the simulation flow. In the demonstration we show the effects of this translation and how it can help to improve simulation coverage.
Keywords
formal verification; IEV; formal analysis; simulation flow; verification closure; Analytical models; Measurement; Simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods in Computer-Aided Design (FMCAD), 2010
Conference_Location
Lugano
Print_ISBN
978-1-4577-0734-6
Electronic_ISBN
978-0-9835678-0-6
Type
conf
Filename
5770959
Link To Document