DocumentCode
545808
Title
An optimized bus arbitration scheme in multiprocessor SoC
Author
Zhikui, Li ; Zhenger, Yao
Author_Institution
Zhejiang Ind. of Polytech. Coll., Shaoxing, China
fYear
2011
fDate
20-22 April 2011
Firstpage
1
Lastpage
4
Abstract
A scheme to optimize bus arbitration for multiprocessor SoC is proposed. This Arbitration combines bus task priority adjustment with task property modification. At first, the allowed execution time window is extended with the guarantee of realtime requirement. Then priorities of original tasks are dynamically adjusted. With our approaches, the idle bus time can be fully utilized to execute the subtasks and thus the conflicts among bus tasks are reduced significantly. Experiments show that processor performance loss is reduced.
Keywords
hardware-software codesign; multiprocessing systems; system-on-chip; bus arbitration scheme; bus task priority adjustment; multiprocessor SoC; task property modification; Decoding; Media; Processor scheduling; Random access memory; Real time systems; Scheduling; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference Proceedings (CJMW), 2011 China-Japan Joint
Conference_Location
Hangzhou
Print_ISBN
978-1-4577-0625-7
Electronic_ISBN
978-7-308-08555-7
Type
conf
Filename
5774066
Link To Document