A Systolic Array Based GTD Processor With a Parallel Algorithm

Generalized triangular decomposition (GTD) has been found to be useful in the field of signal processing, but the feasibility of the related hardware has not yet been established. This paper presents (for the first time) a GTD processor architecture with a parallel algorithm. The proposed parallel GTD algorithm achieves an increase in speed of up to 1.66 times, compared to the speed of its conventional sequential counterpart for an 8 ×8 matrix. For hardware implementation, the proposed reconfigurable architecture is capable of computing singular value decomposition (SVD), geometric mean decomposition (GMD), and GTD for matrix sizes from 1 ×1 to 8 ×8. The proposed GTD processor is composed of 16 processing cores in a heterogeneous systolic array. Computations are distributed over area-efficient coordinate rotation digital computers (CORDICs) to achieve a high throughput. To establish the validity of the concept, a GTD processor was designed and implemented. The latency constraint of 16 μs specified in the 802.11ac standard is adopted for the hardware realization. The proposed design achieves a maximum throughput of 83.3k matrices/s for an 8 ×8 matrix at 112.4 MHz. The estimated power and core area are 172.7 mW and 1.96 mm², respectively, based on standard 90 nm CMOS technology.