High speed architecture of arithmetic coder

A high speed arithmetic coder architecture is proposed in this paper. An out-of-order execution mechanism for different types of context is used that can allocate the context symbol to the idle arithmetic coding core with a different order compared with the input order. For the balance of the input rate of contexts, in one arithmetic coder, there exist N cores for processing different contexts, where N is the number of context type. Furthermore, the same bit detection (SBD) circuit is used for unrolling the renormalization stage of arithmetic coding. Moreover, because of time consuming for underflowing, a dedicated circuit is designed to unrolling the internal loop which can process underflowing situation in a few clock cycles. Experimental results demonstrate that the proposed architecture attains a throughput of 375.50 MCPS (Mega Contexts per Second) at its maximum based on field programmable gate arrays (FPGAs).