Title :
A 10-Bit 100-MSample/s pipelined analog-to-digital converter using digital calibration technique
Author :
Moosazadeh, Tohid ; Yavari, Mohammad
Author_Institution :
Dept. of Electr. Eng., Amirkabir Univ. of Technol., Tehran, Iran
Abstract :
This paper presents a 10-bit 100-Msample/s pipelined analog-to-digital converter (ADC) using the foreground mode of calibration technique proposed in [1]. This technique can overcome the capacitors mismatch, gain error, and amplifier nonlinearities. Simulation results show that the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 64 dB, a peak spurious-free dynamic range (SFDR) of 74 dB, a differential nonlinearity (DNL) of 0.12 least significant bit (LSB) and a integral nonlinearity (INL) of 0.3 LSB for a sinusoidal input signal with 30 MHz frequency. The ADC core (without calibration circuitry) consumes 27mW power from a 1V supply voltage in a 90-nm CMOS technology.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; calibration; ADC core; CMOS technology; amplifier nonlinearities; calibration circuitry; capacitor mismatch; differential nonlinearity; digital calibration technique; frequency 30 MHz; gain error; integral nonlinearity; least significant bit; pipelined analog-digital converter; signal-to-noise-and-distortion ratio; sinusoidal input signal; size 90 nm; spurious-free dynamic range; voltage 1 V; word length 10 bit; CMOS integrated circuits; Calibration; Capacitors; Gain; Solid state circuits; Switches; Timing; Pipelined ADCs; amplifier nonlinearities; capacitor mismatch; digital calibration; gain error;
Conference_Titel :
Electrical Engineering (ICEE), 2011 19th Iranian Conference on
Conference_Location :
Tehran
Print_ISBN :
978-1-4577-0730-8
Electronic_ISBN :
978-964-463-428-4
