FPGA implementation of JPEG-LS compression algorithm for real time applications

This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has increased to 155.2 MHz and any 512×512 pixel image can be compressed in less than 1700 us at these frequency and architecture. Compressor architecture was described by VerilogHDL and implemented on ALTERA Stratix II FPGA.