An optimized high gain CMOS LNA using simulated annealing and modified genetic algorithm

This paper proposes two simulation-based evolutionary and statistical approaches for designing a 18 GHz Low Noise Amplifier (LNA) with using 0.13 μm technology. Based on genetic algorithm (GA), simulated annealing (SA), the Levenberg-Marquardt (LM), and circuit simulator, the simulation-based methods simultaneously optimize the electrical specifications, such as S-parameters, the noise figure, and the input-referred third-order intercept point in the process. In the designed LNA, the structure of one-stage cascode amplifier with source inductive degeneration is used. This LNA draws 12 mA from the 1.2 V power supply. The LNA demonstrates 17.62 dB for S₂₁ and 18.6 dB for MAG at the peak gain frequency of 17.49 GHz. The optimized simulation results show that the proposed LNA has a noise figure (NF) of 1.8 dB in the 17.49 GHz frequency. For large input signal level, P_1dB, OIP3, and IIP3 are: -8 dBm, +23 dBm and +11 dBm, respectively.