Resolution enhanced latch comparator

A new low offset and high speed latch comparator is presented. The proposed offset compensation technique enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. In order to enhance the loop gain of offset cancellation feedback the latch negative resistance is used. The Monte-Carlo simulation results for the designed comparator in 0.18μm CMOS process show that equivalent input referred offset voltage is 0.2mV at 1 sigma while it was 26mV at 1 sigma before offset cancellation. The comparator operates in 500MHz clock frequency while dissipates 600μW from a 1.8V supply.