Title :
A duty cycle corrector based frequency multiplier
Author :
Navidi, Mir Mohammad ; Abrishamifar, Adib
Author_Institution :
Iran Univ. of Sci. & Technol., Tehran, Iran
Abstract :
In this paper a modified frequency multiplier based on a low power duty cycle corrector is presented. The proposed circuit multiplies the output frequency of a PLL, by 3. Also, the output duty cycle of the multiplier could be controlled by changing the ratio of charging/discharging current of the charge pump. This circuit is simulated by using 0.18 um CMOS process. When the VCO operates at 846MHz the power dissipation of the circuit is 1.16mW at 1.8V supply voltage.
Keywords :
CMOS integrated circuits; charge pump circuits; frequency multipliers; low-power electronics; phase locked loops; voltage-controlled oscillators; CMOS process; PLL; VCO; charge pump; charging-discharging current; frequency 846 MHz; frequency multiplier; low power duty cycle corrector; power 1.16 mW; power dissipation; size 0.18 mum; voltage 1.8 V; Duty Cycle Correction; Frequency multiplier; Voltage Controlled Oscillator;
Conference_Titel :
Electrical Engineering (ICEE), 2011 19th Iranian Conference on
Conference_Location :
Tehran
Print_ISBN :
978-1-4577-0730-8
