A new design technique for propagation delay and power reduction in the CML buffers

This paper introduces a method to determine the sizing of the buffers used in the driver of a differential transmission line on chip. Using this technique, the power and delay performance of the buffer is improved, compared with the conventional CML design method. Simulations show that for a differential transmission line with a 138.8 fF capacitive and a 73 Ω resistive load, the power-delay product and the rise-time are improved by 169.3% and 14.3%, respectively. The designs are performed in a typical 90 nm CMOS technology with a 1.2 V power supply.