A new design technique for propagation delay and power reduction in the CML buffers

Author

Javadi, M. ; Masoumi, Nasser ; Sheikhaei, Samad

Author_Institution

Sch. of Electr. & Comput. Eng., Univ. of Tehran, Tehran, Iran

fYear

2011

fDate

17-19 May 2011

Firstpage

1

Lastpage

1

Abstract

This paper introduces a method to determine the sizing of the buffers used in the driver of a differential transmission line on chip. Using this technique, the power and delay performance of the buffer is improved, compared with the conventional CML design method. Simulations show that for a differential transmission line with a 138.8 fF capacitive and a 73 Ω resistive load, the power-delay product and the rise-time are improved by 169.3% and 14.3%, respectively. The designs are performed in a typical 90 nm CMOS technology with a 1.2 V power supply.

Keywords

CMOS logic circuits; buffer circuits; current-mode circuits; current-mode logic; delays; driver circuits; logic design; transmission lines; CML buffers; CML design method; CMOS technology; capacitance 138.8 fF; current mode logic circuits; driver; power reduction; power-delay product; propagation delay; resistance 73 ohm; resistive load; size 90 nm; voltage 1.2 V; CML; CML buffer design; current mode logic; optimization; power and delay reduction; sizing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2011 19th Iranian Conference on

Conference_Location

Tehran

Print_ISBN

978-1-4577-0730-8

Type

conf

Filename

5955851