A new bulk-driven high performance (Differential Static CMOS Logic) DSCL with low capacitive loads

This article proposes an improved structure of conventional Differential Static Circuit Logic (DSCL) using a special kind of bulk-driven method and new loads, called Bulk-Driven Differential Static Circuit Logic (BDDSCL). The circuit topology of the BDDSCL and its performance factors are clarified. The performance of the BDDSCL is compared to the conventional DSCL circuits in terms of delay, power, power-delay-product, output capacitances and output transient current. Delay optimization of the newly BDDSCL studied and it shows the full preserve of static properties in BDDSCL too. The performance evaluation of both circuits was carried out using HSPICE simulations, 180nm technology and power supply of 1.8v. In the same optimum operational condition, the BDDSCL achieved power-delay-product (PDP), 21.5% less than DSCL Using load No.1, 24.5% utilizing modified Load No.1 and 18.3% reduction of PDP by applying load No.2.