A new low power-delay-product, low-area, parallel prefix adder with reduction of graph energy

Summary from only given. In this paper a new low-power, low-area parallel prefix adder (PPA) is presented. In the target PPA graph, relation between graph energy and electrical energy or power consumption with graph nodes and arcs for PPA structures is studied. The Sklansky adder is selected as the target PPA and its recursion steps limited to maximum 8steps. This reduced the internal nodes of the PPA. The reduction of nodes and arcs and limiting the recursive stages to maximum 8 steps from one side and using special CMOS gates for graph nodes from the second side, resulted in a new low-power PPA structure. All the simulations are done with Hspice and CMOS technology 180nm. Our proposed 32 bits PPA structure reduces PDP about 35% compared to Sklansky adder.