A highly-linear modified pseudo-differential current starved delay element with wide tuning range

This paper describes an efficient structure of a pseudo-differential current starved delay element that is used in a four stages delay line targeted for analog/mixed Delay-Locked-Loops. The designed circuit has been simulated in ADS software, using TSMC 0.18 um CMOS process at 1.5 V supply voltage. Body feed technique is used to widen applicable range of control voltage. The linearity of circuit is, also, improved compared to the conventional current starved delay elements. Moreover, improving the noise performance is achieved by taking advantage of differential structure. The simulation results indicate that tunable delay range of proposed delay cell is within 0.26-1.6 ns. Sweeping the control voltage from 0 to 1.2 V at 350 MHz, the calculated gain is almost 1.11 ns/V. The operation frequency range of the four stages delay line is 180 to 500 MHz. While operating at 350 MHz, the peak-to-peak and rms jitters are 9.5 and 32 ps, respectively, and the maximum power consumption in this frequency is 0.4 mW.