A developed adding and latency reducing method for high speed pipelined adders

Summary from only given. In the majority of the digital designs, adder is the basic building block of the most computational systems. Recently, increasing the speed of adders has been a challenging issue for most of researchers. In this article, a developed adding method is proposed for half adder (HA) based pipeline adders where the output evaluating and latching operations are combined together. As the output functions delay is divided into both halves of clocks, the speed would be enhanced by factor of two. Also a novel algorithm is presented for diminishing the latency of the adders. The adder is operated at 4.76 GHz clock frequency in standard 0.18 μm CMOS technology with 1.8 V supply voltage. Simulations are performed using Hspice (level 49) to compare five high speed adders with different structures. The results validate the effective performance of the proposed method.