Improved post-silicon power modeling using AC lock-in techniques

The objective of power modeling is to estimate the power consumption of integrated circuits under different workloads and variabilities. Post-silicon power modeling is an essential step for design validation and for building trustable pre-silicon power models and analyses. One popular approach for devising post-silicon power estimates is to translate the thermal emissions from the backside of the die into power estimates. Such approach faces a major physical challenge arising from spatial heat diffusion which blurs the resultant thermal images. The objective of this paper is to improve post-silicon power mapping by utilizing lock-in thermography techniques where AC signals, rather than DC signals, are used to excite the circuit blocks. We prove and demonstrate that using AC excitation sources reduces the extent of spatial heat diffusion. We devise a lock-in based thermal to power inversion methodology that maps spatial power consumption on a real chip. Using a custom test chip, we are to able to scientifically quantify and validate the improvements in power mapping attained from the proposed techniques. We show that our technique reduces the power mapping errors by more than half.