High-performance energy-efficient encryption in the sub-45nm CMOS era

Summary form only given. With technology scaling enabling integration of billions of transistors on a single processor core, deploying high-performance and energy-efficient encryption/decryption engines on-die has become a reality in the sub-45nm CMOS era. Not only does this enable increased security of processor platforms, but also achieves unprecedented improvements in power-performance through the adoption of specialized hardware accelerator engines for various compute-intensive cryptography algorithms. In this presentation, we describe novel arithmetic and data-path technologies to enable high-speed on-die AES encryption/decryption accelerators for processor security, Secure Hashing Algorithm (SHA) compute engines, Galois-Field multipliers for public-key cryptography acceleration and secure on-die key generation using fully-digital random number generators based on metastable state elements. Circuit and design optimizations to enable ultra-low voltage operation of these accelerators are discussed to achieve up to a 10X higher energy-efficiency and a wide dynamic operating voltage range that enables scalable AES encryption/decryption down to sub-10mW per round, enabling power-efficient security to permeate into future mobile/hand-held/wearable devices.