Diagnosing scan clock delay faults through statistical timing pruning

A novel methodology for diagnosing the delay faults in the scan clock tree is proposed. The proposed scheme characterizes the timing impact of the defective clock buffers by extracting the change in the delay distribution of the clock paths, enabling the effective pruning of unrealistic fault hypotheses that would result in highly deviant timing behavior. The proposed scheme models the statistical delay variation due to test mode power-ground noise, thus maximally approximating the actual failure behavior. Simulation results have confirmed that the proposed methodology can yield highly accurate diagnosis results for complex fault manifestations.