Error-resilient low-power DSP via path-delay shaping

In this paper, we present a novel circuit-level timing error mitigation technique, which aims to increase energy-efficiency when applying a known in situ error-detection and correction technique, called Razor, to DSP datapaths. Timing errors are detected using Razor flip-flops at critical-path endpoints and the error-rate feedback is used to control a dynamic voltage scaling (DVS) control loop. We propose a new approach to bound the magnitude of intermittent timing errors at the circuit level by introducing a guard-band over which timing errors are safely mitigated. The guard-band is achieved by shaping the path delay distribution such that the critical paths correspond to a group of LSB result registers. These end-points are ensured to be critical by modifying the topology of the final stage carry-merge adder and by using tool-based device sizing. Hence, timing violations lead to weakly correlated logical errors of small magnitude in a mean-squared-error sense. We applied this approach to a digital filter in 32nm CMOS. Power saving compared to a conventional design was 23%, over worst-case process and temperature corners.