Title :
CIRUS: A scalable modular architecture for reusable drivers
Author_Institution :
Principal Engineer and Manager, SW Reuse and Convergence, SoC Enabling Group, Intel Corporation, USA
Abstract :
The system on a chip (SoC) market segment is driven by rapid TTM (time to market), OS scalability, and efficiency. This requires the SW stack to be designed with TTM, scalability and efficiency as first order design constraints. In this paper we propose a layered modular architecture for SoC drivers to enable aggressive driver code reuse between OSes and platforms. This cuts SW development, validation, integration, and maintenance effort. We then discuss the implementation of such an architecture in a media driver that is highly reusable across SoCs in different market segments and operating systems.
Keywords :
driver circuits; system-on-chip; CIRUS; OS scalability; SoC drivers; aggressive driver code reuse; layered modular architecture; market segment; rapid TTM; reusable drivers; scalable modular architecture; system on a chip; time to market; Computer architecture; Maintenance engineering; Media; Operating systems; Scalability; System-on-a-chip; System-on-a-chip; architecture; drivers; modular; reusable;
Conference_Titel :
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location :
New York, NY
Print_ISBN :
978-1-4503-0636-2
