Title :
New sub-20nm transistors — Why and how
Author_Institution :
Dept. of EECS, Univ. of California, Berkeley, CA, USA
Abstract :
Two new MOSFET structures are candidates for sub-20nm IC technologies according to International Technology Roadmap for Semiconductors. FinFET and UTB-SOI transistors are poised to replace today´s MOSFETs and will provide much needed relief to ICs from their power and device variation predicaments.
Keywords :
MOSFET; integrated circuit design; semiconductor device models; silicon-on-insulator; FinFET; IC technologies; International Technology Roadmap for Semiconductors; MOSFET structures; UTB-SOI transistors; device variation; size 20 nm; Films; FinFETs; Integrated circuits; Logic gates; MOSFET circuits; Silicon; ETSOI; FDSOI; FinFET; Low-power; MOSFET; Scaling; Transistor; Tri-gate; UTB-SOI; non-planar;
Conference_Titel :
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location :
New York, NY
Print_ISBN :
978-1-4503-0636-2
