Title :
Dynamic effort scaling: Managing the quality-efficiency tradeoff
Author :
Chippa, Vinay ; Raghunathan, Anand ; Roy, Kaushik ; Chakradhar, Srimat
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
Several recently proposed design techniques leverage the inherent error resilience of applications for improved efficiency (energy or performance). Hardware and software systems that are thus designed may be viewed as “scalable effort systems”, since they offer the capability to modulate the effort that they expend towards computation, thereby allowing for tradeoffs between output quality and efficiency. We propose the concept of Dynamic Effort Scaling (DES), which refers to dynamic management of the control knobs that are exposed by scalable effort systems. We argue the need for DES by observing that the degree of resilience often varies significantly across applications, across datasets, and even within a dataset. We propose a general conceptual framework for DES by formulating it as a feedback control problem, wherein the scaling mechanisms are regulated with the goal of maintaining output quality within a certain specified limit. We present an implementation of Dynamic Effort Scaling in the context of a scalable-effort processor for Support Vector Machines, and evaluate it under various application scenarios and data sets. Our results clearly demonstrate the benefits of the proposed approach - statically setting the scaling mechanisms leads to either significant error overshoot or significant opportunities for energy savings left on the table unexploited. In contrast, DES is able to effectively regulate the output quality while maximally exploiting the time-varying resiliency in the workload.
Keywords :
circuit feedback; microprocessor chips; scaling circuits; support vector machines; control knobs; dynamic effort scaling; dynamic management; error overshoot; feedback control problem; gardware systems; inherent error resilience; quality-efficiency tradeoff; scalable effort systems; scalable-effort processor; scaling mechanisms; software systems; support vector machines; time-varying resiliency; Computer architecture; Hardware; Latches; Resilience; Sensors; Support vector machines; Voltage control; Approximate Computing; Dynamic Effort Scaling; Low Power Design; Mining; Recognition; Scalable Effort; Support Vector Machines;
Conference_Titel :
Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE
Conference_Location :
New York, NY
Print_ISBN :
978-1-4503-0636-2