Power-gated MOS Current Mode Logic (PG-MCML): A power aware DPA-resistant standard cell library

MOS Current Mode Logic (MCML) is one of the most promising logic style to counteract power analysis attacks. Unfortunately, the static power consumption of MCML standard cells is significantly higher compared to equivalent functions implemented using static CMOS logic. As a result, the use of such a logic style is very limited in portable devices. Paradoxically, these devices are the most sensitive to physical attacks, thus the ones which would benefit more from the adoption of MCML. We propose to overcome this limitation by reducing drastically the static power consumption of MCML-based cryptographic circuits. To this end, we designed Power Gated MCML (PG-MCML), a standard cell library featuring a sleep transistor in every cell. The effects of the sleep transistor on performance as well as on area are negligible. Moreover, the proposed differential library is supported by conventional EDA tools. We evaluated our standard cell library using Advanced Encryption Standard (AES) as benchmark and we compared the power consumption, the area, and the DPA-resistance figures with the ones of static CMOS and conventional MCML. Our results show that our PG-MCML library can achieve a power consumption comparable with the one of static CMOS, thus proving that PG-MCML cells can suit the strict power budget of battery operated devices.