A highly scalable vertical gate (VG) 3D NAND Flash with robust program disturb immunity using a novel PN diode decoding structure

Author

Hung, Chun-Hsiung ; Lue, Hang-Ting ; Chang, Kuo-Pin ; Chen, Chih-Ping ; Hsiao, Yi-Hsuan ; Chen, Shih-Hung ; Shih, Yen-Hao ; Hsieh, Kuang-Yeu ; Yang, Mars ; Lee, James ; Wang, Szu-Yu ; Yang, Tahone ; Chen, Kuang-Chao ; Lu, Chih-Yuan

Author_Institution

Emerging Central Lab., Macronix Int. Co. Ltd., Hsinchu, Taiwan

fYear

2011

fDate

14-16 June 2011

Firstpage

68

Lastpage

69

Abstract

A novel PN diode decoding method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming pulse waveform is integrated to implement the program-inhibit method, capitalizing on that the PN diodes can prevent leakage of the self-boosted channel potential. A large program-disturb-free window >;5V is demonstrated.

Keywords

NAND circuits; decoding; flash memories; PN diode decoding structure; highly scalable vertical gate 3D NAND flash; highly symmetrical cell structure; program-disturb-free window; program-inhibit method; robust program disturb immunity; scalable cell structure; self-boosted channel potential; three-step programming pulse waveform; Arrays; Logic gates; Microprocessors; Programming; Three dimensional displays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984513