Sub-25nm FinFET with advanced fin formation and short channel effect engineering

Author

Yamashita, T. ; Basker, V.S. ; Standaert, T. ; Yeh, C.-C. ; Yamamoto, T. ; Maitra, K. ; Lin, C.-H. ; Faltermeier, J. ; Kanakasabapathy, S. ; Wang, M. ; Sunamura, H. ; Jagannathan, H. ; Reznicek, A. ; Schmitz, S. ; Inada, A. ; Wang, J. ; Adhikari, H. ; Ber

Author_Institution

IBM Res., Albany Nano Tech, Albany, NY, USA

fYear

2011

fDate

14-16 June 2011

Firstpage

14

Lastpage

15

Abstract

FinFET devices achieving N/P Ion values of 1250/950 uA/um at 100 nA/um at 1V, 1300/1000 uA/um with self-heating correction, are demonstrated, using a dual work function gate-first process flow at 100 nm gate pitch and 40 nm fin pitch. Ring-oscillator (RO, FO = 3) functionality has been demonstrated, showing excellent Vdd scalability. We have also demonstrated logic scan chain functionality and yield improvement by optimizing the gate stack process. An optimized SIT process has been developed to improve short-channel characteristics in devices with a small number of fins in a narrow active area, which is also critical for manufacturability improvement. Various conformal doping techniques for NFET/PFET are optimized to improve device performance.

Keywords

MOSFET; oscillators; FinFET devices; NFET-PFET; advanced fin formation; conformal doping techniques; dual work function gate-first process flow; logic scan chain functionality; manufacturability improvement; optimized SIT process; ring-oscillator functionality; self-heating correction; short channel effect engineering; size 25 nm; yield improvement; Annealing; Degradation; Doping; FinFETs; Logic gates; Performance evaluation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984610