Title :
A 28nm poly/SiON CMOS technology for low-power SoC applications
Author :
Liang, C.W. ; Chen, M.T. ; Jenq, J.S. ; Lien, W.Y. ; Huang, C.C. ; Lin, Y.S. ; Tzau, B.J. ; Wu, W.J. ; Fu, Z.H. ; Wang, I.C. ; Chou, P.Y. ; Fu, C.S. ; Tzeng, C.Y. ; Chiu, K.L. ; Huang, L.S. ; You, Jian Wei ; Hung, J.G. ; Cheng, Z.M. ; Hsu, B.C. ; Wang, H.
Author_Institution :
Adv. Technol. Div. of Logic, United Microelectron. Corp. Ltd. (UMC), Tainan, Taiwan
Abstract :
This paper presents a state-of-the-art 28 nm CMOS technology using conventional poly gate and SiON gate dielectric (Poly/SiON) with best-in-the-class transistor performance, SRAM SNM (static noise margin), MOM capacitance density and mismatch, and ULK (k = 2.5) interconnect. The ION are 683 and 503 uA/um (at IOFF = 1 nA/um, VDD=1 V) for the n- and p-MOSFET, respectively. (With normalized tOX and VDD, these values are higher than prior publication by 5%/15%). The 6T-SRAM is aggressively scaled to <;0.124 um2 with SNM of 193 mV at 1.0 V and 144 mV at 0.7 V. The via and metal resistances, and the metal-line RC time constants are competitive and well controlled. The characteristics for the RF passive components (MOM capacitor, varactor, and inductor) are also excellent.
Keywords :
CMOS digital integrated circuits; MOSFET; SRAM chips; low-power electronics; system-on-chip; CMOS technology; MOM capacitance density; RF passive components; SRAM SNM; ULK interconnect; best-in-the-class transistor performance; inductor; low-power SoC applications; metal resistance; metal-line RC time constants; p-MOSFET; poly gate-SiON gate dielectric; poly-SiON gate dielectric; size 28 nm; static noise margin; varactor; via resistance; voltage 0.7 V; voltage 1.0 V; voltage 144 mV; voltage 193 mV; Capacitance; Copper; Logic gates; Moment methods; Random access memory; Reliability;
Conference_Titel :
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-9949-6
