Scalable TaN metal source/drain & gate InGaAs/Ge n/pMOSFETs

Author

Maeda, T. ; Urabe, Y. ; Itatani, T. ; Ishii, H. ; Miyata, N. ; Yasuda, T. ; Yamada, H. ; Hata, M. ; Yokoyama, M. ; Takenaka, M. ; Takagi, S.

Author_Institution

Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan

fYear

2011

fDate

14-16 June 2011

Firstpage

62

Lastpage

63

Abstract

We propose a scalable CMOS fabrication process for high mobility InGaAs/Ge dual channels using a common TaN metal source/drain and gate (Metal-SD&G) under consideration of material band lineup. By combining common TaN Metal-SD with compatible TaN/Al₂O₃ gate stacks, we have successfully demonstrated operation of both InGaAs nMOS and Ge pMOS devices fabricated at the same time. Excellent InGaAs/Ge n/pMOSFET performances, such as the SS of 70mV/dec and 100mV/dec for InGaAs nMOS and Ge pMOS, respectively, have been achieved. We have also verified the scalability of TaN Metal-SD&G InGaAs nMOSFETs down to 50nm with high immunity to SCEs.

Keywords

CMOS integrated circuits; III-V semiconductors; MOSFET; elemental semiconductors; gallium compounds; germanium; indium compounds; tantalum compounds; InGaAs-Ge; TaN-Al₂O₃; gate n-pMOSFET; gate stacks; high-mobility dual-channels; material band lineup; scalable CMOS fabrication process; scalable metal source-drain; CMOS integrated circuits; Indium gallium arsenide; Logic gates; MOSFETs; Metals; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984633