Author :
Guillorn, M.A. ; Chang, J. ; Pyzyna, A. ; Engelmann, S. ; Glodde, M. ; Joseph, E. ; Bruce, R. ; Ott, J.A. ; Majumdar, A. ; Liu, F. ; Brink, M. ; Bangsaruntip, S. ; Khater, M. ; Mauer, S. ; Lauer, I. ; Lavoie, C. ; Zhang, Z. ; Newbury, J. ; Kratschmer, E.
Author_Institution :
T.J. Watson Res. Center, IBM Res., Yorktown Heights, NY, USA
Abstract :
We present the highest density demonstration of CMOS technology reported to date featuring a 6T SRAM cell size of 0.021 μm2 (Fig. 1). The motivation for this work was to explore the limits of device patterning and basic module integration at dimensions relevant to the 10 nm node. A trigate device architecture with a minimum contacted gate pitch (CGP) and minimum contacted fin pitch (CFP) of 50 nm was used as the target technology for this demonstration.
Keywords :
CMOS memory circuits; SRAM chips; 6T SRAM cell; CFP; CGP; CMOS technology; aggressively-scaled gate; contacted fin pitch; contacted gate pitch; device patterning; module integration; size 10 nm; size 50 nm; trigate device architecture; Lithography; Logic gates; Optimization; Random access memory; Resists; Silicides;
