• DocumentCode
    549706
  • Title

    Unified understanding of Vth and Id variability in tri-gate nanowire MOSFETs

  • Author

    Saitoh, M. ; Ota, K. ; Tanaka, C. ; Nakabayashi, Y. ; Uchida, K. ; Numata, T.

  • Author_Institution
    Adv. LSI Technol. Lab., Toshiba Corp., Yokohama, Japan
  • fYear
    2011
  • fDate
    14-16 June 2011
  • Firstpage
    132
  • Lastpage
    133
  • Abstract
    We present the systematic study of Vth and Idlin/Idsat variability of nanowire transistors (NW Tr.) with various parameters (NW width (WNW) and height (HNW) down to 10nm, NW number (NNW), NW directions, channel dopants). By adopting NW circumference as Weff, the universal line appears in Pelgrom plot of both σVth and σId for a wide range of gate length (Lg), WNW and HNW. We found Avt reduction in NW Tr. compared to planar SOI Tr. due to gate grain alignment. Deviation of σVth and σIdlin of the narrowest Tr. from the universal line was eliminated by suppressing the parasitic resistance (RSD). σIdsat and σIdlin in NW Tr. can be reduced by improving the surface-roughness-limited mobility and its variations, respectively.
  • Keywords
    MOSFET; nanowires; silicon-on-insulator; NW circumference; Pelgrom plot; gate grain alignment; gate length; nanowire transistor variability; parasitic resistance; planar SOI transistors; surface-roughness-limited mobility; trigate nanowire MOSFET; Annealing; Fabrication; Fluctuations; Logic gates; Resistance; Strain; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSIT), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    0743-1562
  • Print_ISBN
    978-1-4244-9949-6
  • Type

    conf

  • Filename
    5984644
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549706