DocumentCode
549720
Title
Design enablement for yield and area optimization at 20 nm and below
Author
Brotman, Andrew ; Capodieci, Luigi ; Liu, Bill ; Rashed, Mahbub ; Kye, Jongwook ; Kengeri, Subramani ; Venkatesan, Suresh
Author_Institution
GLOBALFOUNDRIES, Milpitas, CA, USA
fYear
2011
fDate
14-16 June 2011
Firstpage
108
Lastpage
109
Abstract
There are challenges at 20 nm and below to maintain node to node area reduction and also enable a fast yield ramp and high yield to enable cost scaling. GLOBALFOUNDRIES uses special constructs to reduce cell area along with rule based, model based and pattern based design for manufacturing (feed back from manufacturing to design) and design enabled manufacturing (feed forward from design to manufacturing) in order to achieve these goals.
Keywords
design for manufacture; integrated circuit design; GLOBALFOUNDRIES; area optimization; cost scaling; design enablement; model-based design; node-to-node area reduction; pattern-based design; rule-based design; size 20 nm; yield optimization; Layout; Libraries; Manufacturing; Metrology; Optimization; Predictive models; Process control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4244-9949-6
Type
conf
Filename
5984663
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