DocumentCode
549722
Title
Design technology co-optimization in technology definition for 22nm and beyond
Author
Northrop, Greg
Author_Institution
Semicond. R&D Center, IBM, East Fishkill, NY, USA
fYear
2011
fDate
14-16 June 2011
Firstpage
112
Lastpage
113
Abstract
The successful scaling of CMOS technology through many generations has carried with it an implicit assumption that the most effective geometries for assembling circuits does not change significantly. As the ability to scale the physical dimensions becomes increasingly difficult in patterning and process, this assumption no longer leads to an optimal solution. This paper reviews a pragmatic process combining the design and technology development disciplines to optimize the technology definition, particularly in the critical levels design rules, as early in the definition process as possible.
Keywords
CMOS integrated circuits; circuit optimisation; integrated circuit design; CMOS technology scaling; assembling circuits; critical-level design rules; design technology cooptimization; patterning; pragmatic process; CMOS integrated circuits; CMOS technology; Integrated circuit interconnections; Layout; Lithography; Logic gates; Wiring; CMOS; RDR; design rule; lithography; scaling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
0743-1562
Print_ISBN
978-1-4244-9949-6
Type
conf
Filename
5984665
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