Ultra-thin buried nitride integration for multi-VT, low-variability and power management in planar FDSOI CMOSFETs

Author

Nguyen, P. ; Andrieu, F. ; Garros, X. ; Widiez, J. ; Molas, G. ; Tisseur, R. ; Weber, O. ; Toffoli, A. ; Allain, F. ; Lafond, D. ; Dansas, H. ; Tabone, C. ; Brévard, L. ; Dechamp, J. ; Guiot, E. ; Faynot, O.

Author_Institution

CEA-LETI, Grenoble, France

fYear

2011

fDate

14-16 June 2011

Firstpage

164

Lastpage

165

Abstract

We highlight an original solution to adjust the threshold voltage (V_T) of Fully Depleted Silicon-On-Insulator CMOS down to L=20nm gate length thanks to charge storage in a thin buried nitride layer. In particular, high performance pMOS with I_off=500nA/μm (V_T=-0.2V) are demonstrated in a gate first approach. This technique is combined with back-bias for power management and with a smart process compensation technique to improve the device variability down to σ_VT=4mV for L=30nm and W=500nm.

Keywords

CMOS integrated circuits; MOSFET; silicon-on-insulator; charge storage; device variability; fully-depleted silicon-on-insulator CMOS; high-performance pMOS; planar FDSOI CMOSFET; power management; size 20 nm; size 30 nm; size 500 nm; smart process compensation technique; threshold voltage; ultrathin buried nitride integration; voltage -0.2 V; voltage 4 mV; Bismuth; CMOS integrated circuits; Hot carrier injection; Logic gates; MOS devices; Performance evaluation; Substrates;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

0743-1562

Print_ISBN

978-1-4244-9949-6

Type

conf

Filename

5984686