Title :
Offset buried metal gate vertical floating body memory technology with excellent retention time for DRAM application
Author :
Hwang, Sang-Min ; Banna, Srinivasa ; Tang, Cathy ; Bhardwaj, Sunil ; Gupta, Mayank ; Thurgate, Tim ; Kim, David ; Kwon, Jungtae ; Kim, Joong-Sik ; Lee, Seung-Hwan ; Lee, J.-Y. ; Chung, S.-J. ; Park, J.-W. ; Chung, Sung-Woong ; Cho, S.-H. ; Roh, J.-S. ; Le
Author_Institution :
R&D Div., Hynix Semicond. Inc., Icheon, South Korea
Abstract :
Offset buried metal gate vertical floating body (FB) memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating window (OW) is improved by 75%, while static and disturb tRET @ 1.3V, T=93C are >; 10x better than our previous work [1]. Array measurements and TCAD results confirm that maximum junction electric field (Emax) reduction is the primary reason for tRET improvement.
Keywords :
DRAM chips; electronic design automation; technology CAD (electronics); FB memory cell technology; TCAD results; array measurements; maximum junction electric field reduction; offset buried metal gate vertical floating body memory technology; operating window; recess gate DRAM technology; retention time; tRET improvement; voltage 1.3 V; Arrays; Implants; Junctions; Logic gates; Metals; Random access memory; Very large scale integration; 1T-DRAM; Floating body cell;
Conference_Titel :
VLSI Technology (VLSIT), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-4244-9949-6
