DocumentCode :
549797
Title :
3D stackable 32nm High-K/Metal Gate SOI embedded DRAM prototype
Author :
Golz, John ; Safran, John ; He, Bishan ; Leu, Derek ; Yin, Ming ; Weaver, Todd ; Vehabovic, Adis ; Sun, Yan ; Cestero, Alberto ; Himmel, Ben ; Maier, Gary ; Kothandaraman, Chandrasekharan ; Fainstein, Daniel ; Barth, John ; Robson, Norman ; Kirihata, Tosh
Author_Institution :
Syst. & Technol. Group, IBM, Hopewell Junction, NY, USA
fYear :
2011
fDate :
15-17 June 2011
Firstpage :
228
Lastpage :
229
Abstract :
For the first time we report a high performance embedded DRAM prototype fabricated in a 3D stackable 32nm High-K/Metal Gate technology with copper through-silicon vias. Post through-via processing functional test demonstrates that <;1.5ns latency and 500 MHz operation are preserved.
Keywords :
DRAM chips; copper; embedded systems; high-k dielectric thin films; silicon-on-insulator; three-dimensional integrated circuits; 3D stackable high-k SOI embedded DRAM prototype; copper through-silicon vias; high performance embedded DRAM prototype; metal gate SOI embedded DRAM prototype; post through-via processing functional test; size 32 nm; High K dielectric materials; Metallization; Prototypes; Random access memory; Three dimensional displays; Through-silicon vias; 3D; HKMG; TSV; eDRAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
ISSN :
2158-5601
Print_ISBN :
978-1-61284-175-5
Type :
conf
Filename :
5986049
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=549797
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