DocumentCode
549806
Title
A low spur fractional-N digital PLL for 802.11 a/b/g/n/ac with 0.19 psrms jitter
Author
Yao, Chih-Wei ; Lin, Li ; Nissim, Brian ; Arora, Himanshu ; Cho, Thomas
Author_Institution
Marvell Semicond. Inc., Santa Clara, CA, USA
fYear
2011
fDate
15-17 June 2011
Firstpage
110
Lastpage
111
Abstract
A 5.9-to-8.0 GHz fractional-N digital PLL with TDC histogram calibration, reference doubler compensation and non-periodic DCO dithering is implemented in 55nm CMOS. With reference doubled from 40 MHz, the rms jitter integrated from 1kHz to 10MHz is 0.19ps or 0.4° for a 5825 MHz clock measured at TX output, and the in-band noise floor is -108 dBc/Hz. The reference and worst-case fractional spurs are -94dBc and -70dBc, respectively, and it draws 36mW.
Keywords
CMOS integrated circuits; digital phase locked loops; oscillators; wireless LAN; 802.11 a/b/g/n/ac; CMOS; TDC histogram calibration; frequency 1 kHz to 10 MHz; frequency 40 MHz; frequency 5.9 GHz to 8.0 GHz; frequency 5825 MHz; low spur fractional-N digital PLL; nonperiodic DCO dithering; power 36 mW; reference doubler compensation; size 55 nm; time 0.19 ps; Calibration; Clocks; Computer architecture; GSM; Phase locked loops; Phase noise; ADPLL; DCO; TDC and WiFi; digital PLL;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986061
Link To Document