• DocumentCode
    549807
  • Title

    A −104dBc/Hz in-band phase noise 3GHz all digital PLL with phase interpolation based hierarchical time to digital convertor

  • Author

    Miyashita, Daisuke ; Kobayashi, Hiroyuki ; Deguchi, Jun ; Kousai, Shouhei ; Hamada, Mototsugu

  • Author_Institution
    Toshiba Corp., Kawasaki, Japan
  • fYear
    2011
  • fDate
    15-17 June 2011
  • Firstpage
    112
  • Lastpage
    113
  • Abstract
    An ADPLL which uses a time-to-digital convertor with <;0.13rad resolution achieves LO generation at 3GHz with -104dBc/Hz in-band phase noise. The fine and stable resolution is derived by known phase interpolation circuits. It is fabricated in a 65nm CMOS process and the active area is 0.18mm2.
  • Keywords
    CMOS integrated circuits; convertors; digital phase locked loops; interpolation; phase noise; ADPLL; CMOS process; LO generation; digital PLL; fine resolution; frequency 3 GHz; hierarchical time to digital convertor; in-band phase noise; known phase interpolation circuits; size 65 nm; stable resolution; time-to-digital convertor; Delay; Interpolation; Inverters; Noise measurement; Phase measurement; Phase noise; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986062
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549807