Title :
A 3.6GHz 1MHz-bandwidth ΔΣ fractional-N PLL with a quantization-noise shifting architecture in 0.18µm CMOS
Author :
Chiu, Wei-Hao ; Lin, Tsung-Hsien
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper presents a 3.6GHz ΔΣ fractional-N phase-locked loop (FNPLL) with a quantization-noise shifting (QNS) architecture. The proposed design decreases the amount of the quantization error while effectively increases the modulating frequency; hence, shifting the quantization noise to higher frequency and lower level. Fabricated in a 0.18μm CMOS, the FNPLL achieves -120dBc/Hz at 3MHz offset, with a bandwidth of 1MHz. Measurement results show up to 30dB improvement on quantization noise when QNS mode is activated.
Keywords :
CMOS integrated circuits; phase locked loops; quantisation (signal); CMOS; QNS mode; bandwidth 1 MHz; frequency 3 MHz; frequency 3.6 GHz; modulating frequency; phase-locked loop; quantization error; quantization noise; quantization-noise shifting architecture; size 0.18 mum; Bandwidth; Frequency modulation; Phase frequency detector; Phase locked loops; Phase noise; Quantization;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
