DocumentCode
549809
Title
A 2 GHz fractional-N digital PLL with 1b noise shaping ΔΣ TDC
Author
Jee, Dong-Woo ; Seo, Young-Hun ; Park, Hong-June ; Sim, Jae-Yoon
Author_Institution
Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea
fYear
2011
fDate
15-17 June 2011
Firstpage
116
Lastpage
117
Abstract
A 2 GHz fractional-N digital PLL with a single delay cell, noise shaping ΔΣ TDC is implemented in a 0.13μm CMOS. With a simple structure of Δ modulator followed by a charge pump integrator, a wide range TDC input is converted to ΔΣ modulated bit stream. The implemented TDC consumes 1 mA, and the DPLL shows the in-band phase noise of -107 dBc at 500 kHz offset.
Keywords
CMOS digital integrated circuits; delta-sigma modulation; digital phase locked loops; integrated circuit noise; Δ modulator; CMOS; charge pump integrator; fractional-N digital PLL; frequency 2 GHz; in-band phase noise; noise shaping ΔΣ time-digital converter; single delay cell; size 0.13 mum; Delay; Detectors; Modulation; Noise shaping; Phase noise; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location
Honolulu, HI
ISSN
2158-5601
Print_ISBN
978-1-61284-175-5
Type
conf
Filename
5986064
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