Title :
A 12b 3GS/s pipeline ADC with 500mW and 0.4 mm2 in 40nm digital CMOS
Author :
Chen, Chun-Ying ; Wu, Jiangfeng
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Abstract :
A 12 b 3 GS/s 2-way interleaved pipeline ADC is presented. To achieve high speed, multiple internally generated power/ground rails are used with thin-oxide MOS devices. The ADC achieves a SNR of 61 dB and a DNL of -0.4/+0.6 LSB, consumes 500 mW at 3 GS/s and occupies 0.4 mm2 area in 40nm CMOS process.
Keywords :
CMOS digital integrated circuits; analogue-digital conversion; CMOS process; digital CMOS; interleaved pipeline ADC; power 500 mW; power/ground rail; size 40 nm; thin-oxide MOS device; CMOS integrated circuits; Capacitance; Pipelines; Signal to noise ratio; Switches; Switching circuits; Transistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
