• DocumentCode
    549811
  • Title

    An 11b 300MS/s 0.24pJ/conversion-step Double-Sampling Pipelined ADC with on-chip full digital calibration for all nonidealities including memory effects

  • Author

    Miki, Takuji ; Morie, Takashi ; Ozeki, Toshiaki ; Dosho, Shiro

  • Author_Institution
    Strategic Semicond. Dev. Center, Panasonic Corp., Moriguchi, Japan
  • fYear
    2011
  • fDate
    15-17 June 2011
  • Firstpage
    122
  • Lastpage
    123
  • Abstract
    An 11b Double-Sampling Pipelined ADC (DS-PADC) with memory effect calibration is presented. The full digital calibration simplifies the analog circuit, which extends the operation speed over 300MHz. The chip is fabricated in a 40nm CMOS and occupies 0.42mm2 including the calibration logics. The ADC consumes 40mW from a 1.8V supply, and the FoM is 0.24pJ/conversion-step.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; CMOS; analog circuit; calibration logics; conversion-step double-sampling pipelined ADC; memory effect calibration; on-chip full digital calibration; power 40 mW; size 40 nm; voltage 1.8 V; CMOS integrated circuits; Calibration; Capacitance; Gain; Pipelines; Signal to noise ratio; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2011 Symposium on
  • Conference_Location
    Honolulu, HI
  • ISSN
    2158-5601
  • Print_ISBN
    978-1-61284-175-5
  • Type

    conf

  • Filename
    5986067
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=549811