Title :
A 0.63ps resolution, 11b pipeline TDC in 0.13µm CMOS
Author :
Seo, Young-Hun ; Kim, Jun-Seok ; Park, Hong-June ; Sim, Jae-Yoon
Author_Institution :
Pohang Univ. of Sci. & Technol.(POSTECH), Pohang, South Korea
Abstract :
This paper presents the first pipeline TDC based on time-domain 1.5b MDAC stages with a digital-domain residue calibration and a time amplifier gain calibration. The proposed architecture is implemented with an 11b TDC using a 0.13 μm CMOS. The TDC achieves the finest 1b resolution of 0.63ps ever reported in a conversion range of 1.3ns, DNL of ±0.5LSB, and INL of ±2LSB.
Keywords :
CMOS integrated circuits; digital-analogue conversion; pipeline processing; CMOS; MDAC stage; digital-domain residue calibration; pipeline TDC; size 0.13 micron; time amplifier gain calibration; time-to-digital converter; CMOS integrated circuits; Calibration; Delay; Detectors; Linearity; Pipelines; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
