Title :
High-PSRR all-digital delay locked loop with burst update mode and power noise damping scheme
Author :
Kim, Yongju ; Jang, Jaemin ; Moon, Jinyeong ; Lee, Seongjun ; Kwon, Daehan ; Choi, Hongseok ; Park, Geunwoo ; Chung, Byongtae
Author_Institution :
DRAM Design Team, Hynix Semicond., Icheon, South Korea
Abstract :
The proposed all-digital delay locked loop (DLL) eliminates power noise jitter over all frequency range by combining two methods: Burst update mode and power noise damping filter. The design is fabricated in Hynix´s late 30nm DRAM process and tested with DRAM full-chip operations. The jitter of the proposed DLL was measured in a single-para ATE (Automatic Test Equipment). In 1333Mbps, the measured jitter is 34ps at VDD of 1.5V with the operation current of 1.5mA.
Keywords :
DRAM chips; automatic test equipment; circuit noise; delay lock loops; filters; network synthesis; ATE; DLL; DRAM full-chip operations; all-digital delay locked loop; bit rate 1333 Mbit/s; burst update mode; current 1.5 mA; power noise damping filter; single-para automatic test equipment; size 30 nm; voltage 1.5 V; Clocks; Current measurement; Delay; Jitter; Noise; Power filters; Random access memory; DLL; burst mode update; power noise filter;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
