A programmable MEMS-based clock generator with sub-ps jitter performance

Author

Lee, Fred S. ; Salvia, Jim ; Lee, Cathy ; Mukherjee, Shouvik ; Melamud, Renata ; Arumugam, Niveditha ; Pamarti, Sudhakar ; Arft, Carl ; Gupta, Pavan ; Tabatabaei, Sassan ; Garlepp, Bruno ; Lee, Hae-Chang ; Partridge, Aaron ; Perrott, Michael H. ; Assadera

Author_Institution

SiTime, Sunnyvale, CA, USA

fYear

2011

fDate

15-17 June 2011

Firstpage

158

Lastpage

159

Abstract

A MEMS-based clock generator achieves sub-ps jitter in 0.18 um CMOS. Key enabling techniques include a 48 MHz MEMS oscillator, a reference doubler, a linear XOR-based PFD, a switched-resistor loop filter using accumulation mode NMOS varactors, and native NMOS devices with an RC filter. The overall output at 156.25 MHz achieves an integrated phase jitter of 668 fs rms over an integration bandwidth of 10 kHz-20 MHz.

Keywords

CMOS integrated circuits; clocks; micromechanical devices; oscillators; reference circuits; CMOS; MEMS oscillator; NMOS device; RC filter; accumulation mode NMOS varactor; bandwidth 10 kHz to 20 MHz; frequency 156.25 MHz; frequency 48 MHz; integrated phase jitter; integration bandwidth; linear XOR-based PFD; programmable MEMS-based clock generator; reference doubler; size 0.18 mum; sub-ps jitter performance; switched-resistor loop filter; Clocks; Micromechanical devices; Phase frequency detector; Phase locked loops; Phase noise; Resonator filters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2011 Symposium on

Conference_Location

Honolulu, HI

ISSN

2158-5601

Print_ISBN

978-1-61284-175-5

Type

conf

Filename

5986085