Title :
A 21nm high performance 64Gb MLC NAND flash memory with 400MB/s asynchronous toggle DDR interface
Author :
Kim, Chulbum ; Ryu, Jinho ; Lee, Taesung ; Kim, Hyeonggon ; Lim, Jeawoo ; Jeong, Jaeyong ; Seo, Seonghwan ; Jeon, Hongsoo ; Kim, Bokeun ; Lee, InYoul ; Lee, DooSeop ; Kwak, PanSuk ; Cho, Seongsoon ; Yim, Yongsik ; Cho, Changhyun ; Jeong, Woopyo ; Han, Jin
Author_Institution :
Flash Memory Design Team, Samsung Electron., Hwasung, South Korea
Abstract :
A monolithic 64Gb MLC NAND flash based on 21nm process technology has been developed for the first time. The device consists of 4-plane arrays and provides page size of up to 32KB. It also features a newly developed DDR interface that can support up to the maximum bandwidth of 400MB/s. To address performance and reliability, on-chip randomizer, soft data readout, and incremental bit line precharge scheme have been developed.
Keywords :
NAND circuits; asynchronous circuits; flash memories; integrated circuit reliability; monolithic integrated circuits; MLC NAND flash memory; asynchronous toggle DDR interface; bandwidth; byte rate 400 MByte/s; incremental bit line precharge scheme; monolithic MLC NAND flash; on-chip randomizer; plane arrays; reliability; size 21 nm; soft data readout; Arrays; Bandwidth; Flash memory; Random sequences; Sensors; System-on-a-chip;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
