Title :
A 20-Gb/s, 0.66-pJ/bit serial receiver with 2-stage continuous-time linear equalizer and 1-tap decision feedback equalizer in 45nm SOI CMOS
Author :
Proesel, Jonathan E. ; Dickson, Timothy O.
Author_Institution :
T.J. Watson Res. Center, IBM, Yorktown Heights, NY, USA
Abstract :
A power-efficient equalizing serial receiver, including a 2-stage continuous-time linear equalizer (CTLE) and 1-tap decision feedback equalizer (DFE), is reported operating at data rates of up to 20 Gb/s. The DFE adopts a half-rate speculative architecture without explicit summing amplifiers by injecting offset-controlling currents directly into StrongARM sampling latches. At 20 Gb/s, a PCB trace with 26.3 dB of loss is equalized while consuming 13.2 mW (0.66 pJ/bit).
Keywords :
CMOS integrated circuits; decision feedback equalisers; silicon-on-insulator; 1-tap decision feedback equalizer; 2-stage continuous-time linear equalizer; PCB trace; SOI CMOS; bit rate 20 Gbit/s; half-rate speculative architecture; loss 26.3 dB; power 13.2 mW; power-efficient equalizing serial receiver; size 45 nm; CMOS integrated circuits; CMOS technology; Decision feedback equalizers; Latches; Transceivers; Very large scale integration;
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
Print_ISBN :
978-1-61284-175-5
