DocumentCode :
549843
Title :
A 40Gb/s adaptive receiver with linear equalizer and merged DFE/CDR
Author :
Hsieh, Chang-Lin ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear :
2011
fDate :
15-17 June 2011
Firstpage :
208
Lastpage :
209
Abstract :
A 40Gb/s adaptive receiver using a linear equalizer and a merged half-rate DFE/CDR circuit is fabricated in a 65nm process. For a 40Gb/s PRBS of 27-1, the measured jitter of the retimed data is 9.8pspp and 10.7pspp with BER<;10-12 for the channel loss of 6.7dB and 23.5dB, respectively.
Keywords :
adaptive equalisers; decision feedback equalisers; error statistics; synchronisation; BER; adaptive receiver; bit rate 40 Gbit/s; clock-data recovery; decision-feedback equalizer; linear equalizer; loss 23.5 dB; loss 6.7 dB; size 65 nm; Adders; Clocks; Decision feedback equalizers; Jitter; Loss measurement; Receivers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits (VLSIC), 2011 Symposium on
Conference_Location :
Honolulu, HI
ISSN :
2158-5601
Print_ISBN :
978-1-61284-175-5
Type :
conf
Filename :
5986108
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=549843
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