A 40-nm 0.5-V 20.1-µW/MHz 8T SRAM with low-energy disturb mitigation scheme

This paper presents a novel disturb mitigation scheme which achieves low-power and low-voltage operation for a deep sub-micron SRAM macro. The classic write-back scheme overcame a half-select problem and improved a yield; however, the conventional scheme consumed more power due to charging and discharging all write bitlines (WBLs) in a sub block. Our proposed scheme consists of a floating bitline technique and a low-swing bitline driver (LSBD). This scheme decreases active leakage and active power by 33% and 32% at the FF corner, respectively. In other process corners, more active power reduction can be expected. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The proposed scheme achieves 8.8-μW/MHz active energy in a write cycle and 72.8-μW leakage power, which are 35% and 26% better than the conventional write-back scheme. The total energy is 20.1 μW/MHz at 0.5 V in a 50%-read/50%-write operation.